This invention relates to systems including nonvolatile writeable memory. More particularly, this invention relates to interfacing a nonvolatile writeable memory device to an electronic system application.
Many computing systems such as personal computers, automotive and airplane control, cellular phones, digital cameras, and handheld communication devices use nonvolatile writeable memories to store either data, or code, or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories (xe2x80x9cEEPROMsxe2x80x9d) and flash Erasable and Electrically Programmable Read-Only Memories (xe2x80x9cflash EPROMsxe2x80x9d or xe2x80x9cflash memoriesxe2x80x9d). Nonvolatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
The nonvolatile writeable memories often include a plurality of interconnected very large scale integration (VLSI) circuits. These VLSI circuits dissipate power in proportion to the nominal voltage swing of the binary signals applied to the circuits. The industry standard VLSI complementary metal-oxide-semiconductor (CMOS) circuits currently utilize two levels of input/output (I/O) signals, 1.8 volts and 3.0 volts. Generally, in those circuits utilizing the 1.8 volt signal level, a logic low state (logic xe2x80x9c0xe2x80x9d) is represented by a signal level of 0 volts, and a logic high state (logic xe2x80x9c1xe2x80x9d) is represented by a signal level of 1.8 volts. Generally, in those circuits utilizing the 3.0 volt signal level, a logic low state (logic xe2x80x9c0xe2x80x9d) is represented by a signal level of 0 volts, and a logic high state logic xe2x80x9c1xe2x80x9d) is represented by a signal level of 3.0 volts. Therefore, the VLSI CMOS circuits are attractive for use in digital circuits because of lower power consumption. As the rail-to-rail voltage swing of standard CMOS circuits utilizing the 3.0 volt signal level tends to cause such circuits to dissipate excessive amounts of power and energy over CMOS circuits utilizing the 1.8 volt signal level, the 1.8 volt CMOS circuit would be preferred in an application requiring reduced power consumption.
With the size of many electronic products becoming increasingly smaller, many electronic product designers are currently seeking to minimize power consumption. Generally, reducing the overall magnitude of rail-to-rail voltage swings of CMOS circuits allows a reduction in power consumption. Thus, an electronic architecture that would allow and work with lower input voltage swings without drawing leakage current is desirable. However, certain applications of CMOS circuits are actually more efficient in terms of power consumption when operated at higher signal levels. For example, CMOS circuits configured as nonvolatile writeable memory core circuits have better power efficiency when operated at the 3.0 volt I/O signal level and supply voltage compared to those operated at the 1.8 volt I/O signal level and supply voltage. This increased efficiency at the higher I/O signal voltage level is a result of the charge pumps required by the nonvolatile writeable memory. Consequently, an electronic system architectural concept is desired whereby the nonvolatile writeable memory circuits would be allowed to operate with industry standard 1.8 volt and 3.0 volt CMOS I/O signal levels and utilize the optimum core supply voltage for the nonvolatile writeable memory core circuits.
Designers of prior art electronic systems incorporating nonvolatile writeable memory have attempted to reduce the overall system power consumption by running the entire system at the 1.8 volt I/O signal level and supply voltage. This increases the power consumption efficiency of the system exclusive of the nonvolatile writeable memory. However, the nonvolatile writeable memory core memory circuits running at the 1.8 volt I/O signal level have a reduced power consumption efficiency. Thus, to effectively maximize efficiency of the overall electronic system, I/O interface buffers are required which allow the nonvolatile writeable memory core memory circuits to be operated at a 3.0 volt I/O signal level, while the surrounding system CMOS circuitry is operated at a 1.8 volt I/O signal level. The 3.0 volt I/O nominal signal level can be approximately in the range 2.7 volts to 3.6 volts.
Designers of prior art I/O interface circuitry have attempted to use 1.8 volt I/O signal level buffers while running the nonvolatile writeable memory core memory circuits at a 3.0 volt I/O signal level. Regarding the input buffer portion of the I/O interface, the prior art CMOS input buffers have the input high signal level equal to or within some tolerable specifications to a supply voltage. For the 1.8 volt I/O signal level input buffers, the input high value is substantially lower than the input buffer supply voltage which is typically 3.0 volts. This difference between the input buffer supply voltage, which is also the core supply voltage, and input high voltage signal level, is the source of current leakage and unstable operation of the input buffer.
Furthermore, this current leakage problem limits the flexibility of use of the I/O interface circuitry. This is because anytime there is a difference between the supply voltage and the input high voltage signal level there will be current leakage. Therefore, an input buffer configured to operate with a 1.8 volt I/O signal level cannot be used in a system utilizing 3.0 volt I/O signal levels, and vice versa. This requires separate input buffer configurations to be made available for use in each of the 1.8 and 3.0 volt I/O signal level systems. Moreover, the user does not have the option to run at the higher 3.0 volt CMOS input signal level once a circuit is configured to operate at the 1.8 volt input signal level.
Designers of prior art I/O interface circuitry have attempted to solve this current leakage problem by using one power supply for the 1.8 volt input buffer and a separate power supply for the non-volatile writeable memory core memory circuits operating at the 3.0 volt signal level. This is problematic in that the limits of size and weight imposed by many electronic applications using nonvolatile writeable memory circuits do not allow for the use of more than one power supply.
Regarding the output buffer portion of the I/O interface, the prior art CMOS output buffers have p-channel CMOS drivers, or voltage level pull-ups, driving the output high level equal to or within some tolerable specifications to the supply voltage. For the 1.8 volt I/O signal level output buffers, the lower voltage power supply limits the internal drive capability to meet higher output speed and load requirements in driving a voltage output high level.
Another limitation found in prior art I/O circuitry which can have a significant adverse impact in particular applications is the electrical noise generated by the circuit configuration. In a prior art configuration using a single power supply, the interface circuitry input buffer, nonvolatile writeable memory core memory circuits, and the interface circuitry output buffer of the system are all connected to the same power supply output. In a prior art configuration using separate power supplies for the I/Os and the nonvolatile writeable memory core circuits, the input buffer and the output buffer are connected to the same power supply output. Consequently, in both configurations, the isolation between the input and the output is reduced by having the input and the output connected to the same power supply output. This configuration significantly reduces the noise immunity of the system. This problem is compounded when a system is operated at the 1.8 volt I/O signal level because, at this signal level, the noise margin is decreased. This noise can have significant adverse impacts on performance, particularly in cellular phone applications.
A low-power input buffer for a nonvolatile writeable memory is described. The low-power input buffer accepts input signals having one of a number of pairs of logic levels. The low-power input buffer provides output signals having a pair of logic levels that may differ from the logic levels of the input signal.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description and appended claims that follow below.